Conventionally, in semiconductor integrated circuit devices, output circuits incorporating, as logic signal outputting means, open-drain output transistors are widely used.
Disadvantageously, however, in the output circuit mentioned above, if a sharply rising pulse (such as an electrostatic pulse) is applied to an output terminal (i.e., the drain of the output transistor), the gate potential of the output transistor is raised through parasitic capacitance or the like present between the gate and drain of the output transistor. Thus, the output transistor is erroneously turned on to cause an overcurrent to flow between the source and drain thereof. This may lead to breakdown of the output transistor.
As described above, output circuits incorporating open-drain output transistors offer simple circuit configurations, but disadvantageously have poor resistance to electrostatic breakdown. Thus, conventional semiconductor integrated circuit devices adopt various configurations designed to reduce the overcurrent described above, such as those where, as means for protecting output transistors from electrostatic breakdown, a current-limiting resistor is provided between the drain of the output transistor and an output terminal, or a clamp circuit like a Zener diode is provided between the gate of the output transistor and ground.
As another conventional technology related to the present invention, the applicant of the invention discloses and proposes an output circuit (see patent document 1 below) including a switch circuit that operates when the potential difference between an output terminal and a power line is beyond a predetermined level; when this switch circuit operates, an output transistor is driven to conduct between ground and the output terminal.
Patent document 1: JP-A-H02-274124